IBM announced new servers using the newest POWER7+ chip in October 2012. The plus (+) designation is an approach IBM has used before; most recently with the POWER6+, and before that with POWER5+, to signify chip enhancements short of a full chip revision. POWER7+ provides some substantial improvements, but those expecting POWER8, which IBM has been telegraphing for months, will be disappointed. Still, there’s much in POWER7+ to help Power shops improve overall system performance.
POWER7+ today is the most powerful chip IBM offers in the Power line. The plus version increases the number of virtual machines from 10 to 20 per core while it correspondingly decreases the minimum processor resource to 5 percent for software development. Each core experiences up to 25 percent frequency gain due to mapping into 32nm technology. The chip designers also increased the L3 memory capacity by 2.5 times, doubled single precision floating-point performance, and added POWER Gating regions for Core/L2 and L3 regions to increase granularity for power management purposes.
The POWER7+ runs eight processor cores with 12 execution units per core. It delivers four-way Symmetrical Multi-Threading (SMT) per core with 32 threads per chip (four threads multiplied by eight cores) and 360GB per second Symmetric Multiprocessing (SMP) bandwidth/chip. It provides 256KB of L2 cache per core and 80MB (10MB per core) of on-chip embedded Dynamic Random Access Memory (eDRAM) for shared L3 cache.
As it did with previous recent plus variations, IBM may release versions of POWER7+ with their clocks turned way down so two processors can be squeezed into a single Power server socket, a technique referred to as double-stuffing. This isn’t available now but may become available in a few months, according to Satya Sharma, a senior IBM chip designer.
The chip includes 2.1 billion transistors and runs at up to 4.42 GHz. It also features an added Dynamic Platform Optimizer, an Active Memory Expansion Accelerator (see “Tuning POWER7 Active Memory Expansion for SAP” at http://esmpubs.com/k5t1o) and on-chip encryption for its AIX operating system (the Power series also runs iOS and Linux).
POWER7+ offers easy growth via Capacity on Demand (CoD) and has added more flexible elastic CoD (on/off CoD) enablement keys, allowing for what amounts to utility pricing. You will have to check with IBM for any initial day credits or any no-charge processor and memory day credits. Finally, POWER7+ comes with a slew of accelerators and is binary-compatible with POWER6/7.
POWER7+ has 13 different metal levels (almost as many as the zEC12 chip). The multiple metal levels help minimize cross-die latency but offer nothing a system administrator can use to tweak system performance. The 32nm die allows for the logic transistors to have three different threshold voltages, which enabled IBM to optimize each part of the POWER7+ chip for power and performance.
Finally, IBM has built in several accelerators that offload work from the CPU and speed performance of Secure Sockets Layer (SSL), encrypted file system and Active Memory Expansion (AME). They include:
• Accelerator for Asymmetric Math Functions (AMF) for use with Rivest, Shamir, Adleman (RSA) cryptography and Elliptic Curve Cryptography (ECC)
• Advanced Encryption Standard (AES)/Secure Hash Algorithm (SHA) for use with symmetric-key cryptography with combinational modes
• Random Number Generator (RNG) that provides a true hardware entropy generator that can’t be algorithmically reverse-engineered
• High-bandwidth and an area-efficient 842 proprietary compression algorithm (842 refers to the 8-byte, 4-byte and 2-byte parsings the algorithm supports for memory compression).
All these accelerators are integrated across silicon, Industry Standard Architecture (ISA), hypervisor and the operating system.